The nth degree function is usually represented as f(x)=a.sub.0 +a.sub.1 .multidot.x+a.sub.2 .multidot.x.sup.2 + . . . +a.sub.n .multidot.x.sup.n. In this formula, the zero degree term (the initial term) a.sub.0 is a constant, the first degree term a.sub.1 .multidot.x is a product of coefficient a.sub.1 and variable x, the second degree item a.sub.2 .multidot.x.sup.2 is a product of coefficient a.sub.2 and the square of variable x, x.sup.2, . . . , and the nth degree term is a product of coefficient a.sub.n and the nth power of variable x, x.sup.n. The nth degree function f(x) is a sum of these n items.
As an example, FIG. 10 illustrates the circuit configuration of a conventional second degree function computing device for the second degree function f(x)=a.sub.0 +a.sub.1 .multidot.x+a.sub.2 .multidot.x.sup.2. This second degree function computing device is made up of three multipliers 202, 204, 206 and two adders 208, 210. The values of the coefficients of the various items, a.sub.2, a.sub.1, and a.sub.0, are sent from coefficient generator (not shown in the figure) to one of the input terminals of multipliers 204, 206 and adder 210.
The value of variable x input to device input terminal 200 is sent to the two input terminals of multiplier 202 and the second input terminal of multiplier 204. At multiplier 204, multiplication is performed between x.sup.2, fed from multiplier 202, and a.sub.2, fed from coefficient generator, and the product a.sub.2 .multidot.x.sup.2 is output. Output of multiplier 204, a.sub.2 .multidot.x.sup.2 is fed to one input terminal of adder 208.
On the other hand, at multiplier 206, multiplication is performed between x, fed from device input terminal 200, and a.sub.1, fed from the coefficient generator, and product a.sub.1 .multidot.x is output. The output a.sub.1 .multidot.x of multiplier 206 is sent to the second input terminal of adder 208. At adder 208, a.sub.2 .multidot.x.sup.2 from multiplier 204 and a.sub.1 .multidot.x from multiplier 206 are added, and the sum (a.sub.1 .multidot.x+a.sub.2 .multidot.x.sup.2) is output. The output of adder 208 (a.sub.1 .multidot.x+a.sub.2 .multidot.x.sup.2) is sent to the second input terminal of adder 210. At adder 210, (a.sub.1 .multidot.x+a.sub.2 .multidot.x.sup.2) from adder 208 and a.sub.0 from the coefficient generator are added, and the sum (a.sub.0 +a.sub.1 .multidot.x+a.sub.2 .multidot.x.sup.2) is output.
In this second degree function computing device, in the first cycle, multiplier 202 performs the multiplication (x.times.x); in the second cycle, multiplier 204 performs the multiplication (a.sub.2 .times.x.sup.2). In the first and second cycles, multiplier 206 performs multiplication (a.sub.1 .times.x). In the third cycle, adder 208 performs addition (a.sub.1 .multidot.x+a.sub.2 .multidot.x.sup.2). In the fourth cycle, adder 210 performs addition (a.sub.0 +a.sub.1 .multidot.x+a.sub.2 .multidot.x.sup.2). Consequently, for each variable, the total computing time is 4 cycles. Each time, when a variable x is input, the four-cycle computing operation is repeatedly carried out.
For the conventional nth degree function computing device, with respect to the value of input variable x, the values of the various terms, from the first degree term to the nth degree term of the nth degree function f(x)=a.sub.0 +a.sub.1 .multidot.x+a.sub.2 .multidot.x.sup.2 + . . . +a.sub.n x.sup.n, a.sub.i .multidot.x.sup.i, are computed by multipliers, and the sum of the values of the various terms a.sub.i .multidot.x.sup.i and its sum with the initial term a.sub.0 are computed by adders in this circuit configuration. In this circuit configuration, there should be n(n+1)/2 multipliers. As a matter of fact, in the conventional second degree function computing device shown in FIG. 10, three multipliers 202, 204, 206 are used. However, the area occupied by a multiplier is much larger than that used by an adder, and the cost of the former is also much higher. Consequently, the conventional nth degree function computing device is a large circuit, and is very costly.
Also, for the conventional nth degree function computing device, each time a variable x is input, the computing operation starts from the initial (reset) state. Consequently, even in the case when the value of variable x is consecutively incremented, such as 10, 11, 12, . . . , the operation time for one variable (4 cycles in the case of the second degree function) has to be repeated, and high-speed operation becomes impossible.
It is an object of the present invention to provide an nth degree function computing device having a low-cost, small scale circuit in which no multipliers are present, so that the computing operation can be performed at a high speed for the nth degree function when the value of variable x is consecutively incremented.